Inheritance diagram for modm::Nrf24Register:

Public Typedefs
typedef FlagsGroup< Feature_t, DynPd_t, FifoStatus_t, Rpd_t, ObserveTx_t, Status_t, RfSetup_t, SetupRetr_t, SetupAw_t, EnRxAddr_t, EnAA_t, Config_t, InterruptFlag_t >	Flags_t

Public Types
enum	Command : uint8_t { Command::R_REGISTER = 0b00000000, Command::W_REGISTER = 0b00100000, Command::R_RX_PAYLOAD = 0b01100001, Command::W_TX_PAYLOAD = 0b10100000, Command::FLUSH_TX = 0b11100001, Command::FLUSH_RX = 0b11100010, Command::REUSE_TX_PL = 0b11100011, Command::R_RX_PL_WID = 0b01100000, Command::W_ACK_PAYLOAD = 0b10101000, Command::W_TX_PAYLOAD_NOACK = 0b10110000, Command::NOP = 0b11111111 }

enum	Pipe : uint8_t { PIPE_0 = 0b000, PIPE_1 = 0b001, PIPE_2 = 0b010, PIPE_3 = 0b011, PIPE_4 = 0b100, PIPE_5 = 0b101 }

enum	NrfRegister : uint8_t { NrfRegister::CONFIG = 0x00, NrfRegister::EN_AA = 0x01, NrfRegister::EN_RX_ADDR = 0x02, NrfRegister::SETUP_AW = 0x03, NrfRegister::SETUP_RETR = 0x04, NrfRegister::RF_CH = 0x05, NrfRegister::RF_SETUP = 0x06, NrfRegister::STATUS = 0x07, NrfRegister::OBSERVE_TX = 0x08, NrfRegister::RPD = 0x09, NrfRegister::RX_ADDR_P0 = 0x0a, NrfRegister::RX_ADDR_P1 = 0x0b, NrfRegister::RX_ADDR_P2 = 0x0c, NrfRegister::RX_ADDR_P3 = 0x0d, NrfRegister::RX_ADDR_P4 = 0x0e, NrfRegister::RX_ADDR_P5 = 0x0f, NrfRegister::TX_ADDR = 0x10, NrfRegister::RX_PW_P0 = 0x11, NrfRegister::RX_PW_P1 = 0x12, NrfRegister::RX_PW_P2 = 0x13, NrfRegister::RX_PW_P3 = 0x14, NrfRegister::RX_PW_P4 = 0x15, NrfRegister::RX_PW_P5 = 0x16, NrfRegister::FIFO_STATUS = 0x17, NrfRegister::DYNPD = 0x1c, NrfRegister::FEATURE = 0x1d }

enum	Config : uint8_t { PRIM_RX = Bit0, PWR_UP = Bit1, CRC0 = Bit2, EN_CRC = Bit3, MASK_MAX_RT = Bit4, MASK_TX_DS = Bit5, MASK_RX_DR = Bit6 }

enum	EnAA : uint8_t { ENAA_P0 = Bit0, ENAA_P1 = Bit1, ENAA_P2 = Bit2, ENAA_P3 = Bit3, ENAA_P4 = Bit4, ENAA_P5 = Bit5 }

enum	EnRxAddr : uint8_t { ERX_P0 = Bit0, ERX_P1 = Bit1, ERX_P2 = Bit2, ERX_P3 = Bit3, ERX_P4 = Bit4, ERX_P5 = Bit5 }

enum	SetupAw : uint8_t { AW = Bit0 \| Bit1 }

enum	SetupRetr : uint8_t { ARC = Bit0 \| Bit1 \| Bit2 \| Bit3, ARD = Bit4 \| Bit5 \| Bit6 \| Bit7 }

enum	RfCh : uint8_t { RF_CH = Bit0 \| Bit1 \| Bit2 \| Bit3 \| Bit4 \| Bit5 \| Bit6 }

enum	RfSetup : uint8_t { RF_PWR = Bit1 \| Bit2, RF_DR_HIGH = Bit3, PLL_LOCK = Bit4, RF_DR_LOW = Bit5, CONT_WAVE = Bit7 }

enum	Status : uint8_t { TX_FULL = Bit0, RX_P_NO = Bit1 \| Bit2 \| Bit3, MAX_RT = Bit4, TX_DS = Bit5, RX_DR = Bit6 }

enum	ObserveTx : uint8_t { ARC_CNT = Bit0 \| Bit1 \| Bit2 \| Bit3, PLOS_CNT = Bit4 \| Bit5 \| Bit6 \| Bit7 }

enum	Rpd : uint8_t { RPD = Bit0 }

enum	RxPwP0 : uint8_t { RX_PW_P0 = Bit0 \| Bit1 \| Bit2 \| Bit3 \| Bit4 \| Bit5 }

enum	RxPwP1 : uint8_t { RX_PW_P1 = Bit0 \| Bit1 \| Bit2 \| Bit3 \| Bit4 \| Bit5 }

enum	RxPwP2 : uint8_t { RX_PW_P2 = Bit0 \| Bit1 \| Bit2 \| Bit3 \| Bit4 \| Bit5 }

enum	RxPwP3 : uint8_t { RX_PW_P3 = Bit0 \| Bit1 \| Bit2 \| Bit3 \| Bit4 \| Bit5 }

enum	RxPwP4 : uint8_t { RX_PW_P4 = Bit0 \| Bit1 \| Bit2 \| Bit3 \| Bit4 \| Bit5 }

enum	RxPwP5 : uint8_t { RX_PW_P5 = Bit0 \| Bit1 \| Bit2 \| Bit3 \| Bit4 \| Bit5 }

enum	FifoStatus : uint8_t { RX_EMPTY = Bit0, RX_FULL = Bit1, TX_EMPTY = Bit4, TX_FULL = Bit5, TX_REUSE = Bit6 }

enum	DynPd : uint8_t { DPL_P0 = Bit0, DPL_P1 = Bit1, DPL_P2 = Bit2, DPL_P3 = Bit3, DPL_P4 = Bit4, DPL_P5 = Bit5 }

enum	Feature : uint8_t { EN_DYN_ACK = Bit0, EN_ACK_PAY = Bit1, EN_DPL = Bit2 }

enum	InterruptFlag : uint8_t { MAX_RT = Bit4, TX_DS = Bit5, RX_DR = Bit6, ALL = Bit4 \| Bit5 \| Bit6 }

Public Member Functions
	MODM_FLAGS8 (Command)

	MODM_FLAGS8 (Pipe)

	MODM_FLAGS8 (NrfRegister)

	MODM_FLAGS8 (Config)

	MODM_FLAGS8 (EnAA)

	MODM_FLAGS8 (EnRxAddr)

	MODM_FLAGS8 (SetupAw)

	MODM_FLAGS8 (SetupRetr)

	MODM_FLAGS8 (RfCh)

	MODM_FLAGS8 (RfSetup)

	MODM_FLAGS8 (Status)

	MODM_FLAGS8 (ObserveTx)

	MODM_FLAGS8 (Rpd)

	MODM_FLAGS8 (RxPwP0)

	MODM_FLAGS8 (RxPwP1)

	MODM_FLAGS8 (RxPwP2)

	MODM_FLAGS8 (RxPwP3)

	MODM_FLAGS8 (RxPwP4)

	MODM_FLAGS8 (RxPwP5)

	MODM_FLAGS8 (FifoStatus)

	MODM_FLAGS8 (DynPd)

	MODM_FLAGS8 (Feature)

	MODM_FLAGS8 (InterruptFlag)

Member Enumeration Documentation

enum modm::Nrf24Register::Command : uint8_t

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Enum Values	Documentation
R_REGISTER	1 - 5 data bytes \| lower 5 bit = Register address
W_REGISTER	1 - 5 data bytes \| lower 5 bit = Register address
R_RX_PAYLOAD	1 - 32 data bytes
W_TX_PAYLOAD	1 - 32 data bytes
FLUSH_TX	0 data bytes
FLUSH_RX	0 data bytes
REUSE_TX_PL	0 data bytes
R_RX_PL_WID	1 data bytes
W_ACK_PAYLOAD	1 - 32 data bytes \| lower 3 bit = Pipe # (000 to 101)
W_TX_PAYLOAD_NOACK	1 - 32 data bytes
NOP	0 data bytes

enum modm::Nrf24Register::NrfRegister : uint8_t

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Enum Values	Documentation
CONFIG	Configuration Register.
EN_AA	Enable 'Auto Acknowledgment'.
EN_RX_ADDR	Enabled RX Addresses.
SETUP_AW	Setup of Address Widths.
SETUP_RETR	Setup of Automatic Retransmission.
RF_CH	RF Channel.
RF_SETUP	RF Setup Register.
STATUS	Status Register.
OBSERVE_TX	Transmit observe register.
RPD	Received Power Detector.
RX_ADDR_P0	Receive address data pipe 0.
RX_ADDR_P1	Receive address data pipe 1.
RX_ADDR_P2	Receive address data pipe 2.
RX_ADDR_P3	Receive address data pipe 3.
RX_ADDR_P4	Receive address data pipe 4.
RX_ADDR_P5	Receive address data pipe 5.
TX_ADDR	Transmit address.
RX_PW_P0	Number of bytes in RX payload in pipe 0.
RX_PW_P1	Number of bytes in RX payload in pipe 1.
RX_PW_P2	Number of bytes in RX payload in pipe 2.
RX_PW_P3	Number of bytes in RX payload in pipe 3.
RX_PW_P4	Number of bytes in RX payload in pipe 4.
RX_PW_P5	Number of bytes in RX payload in pipe 5.
FIFO_STATUS	FIFO Status Register.
DYNPD	Enable dynamic payload length.
FEATURE	Feature Register.

The documentation for this struct was generated from the following file:

nrf24_definitions.hpp

Public Typedefs

Public Types

Public Member Functions

Member Enumeration Documentation