modm API documentation
|
#include <modm/platform/clock/rcc.hpp>
Classes | |
struct | PllFactors |
Public Types | |
enum | PllSource : uint32_t { PllSource::Hsi = RCC_PLLCFGR_PLLSRC_HSI, InternalClock = Hsi, PllSource::Hse = RCC_PLLCFGR_PLLSRC_HSE, ExternalClock = Hse, ExternalCrystal = Hse } |
enum | SystemClockSource : uint32_t { Hsi = RCC_CFGR_SW_HSI, Hse = RCC_CFGR_SW_HSE, InternalClock = Hsi, ExternalClock = Hse, ExternalCrystal = Hse, Pll = RCC_CFGR_SW_PLL } |
enum | RealTimeClockSource : uint32_t { Lsi = RCC_BDCR_RTCSEL_1, Lse = RCC_BDCR_RTCSEL_0, Hse = RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1, ExternalClock = Hse, ExternalCrystal = Hse, LowSpeedInternalClock = Lsi, LowSpeedExternalClock = Lse, LowSpeedExternalCrystal = Lse } |
enum | WatchdogClockSource : uint32_t { LowSpeedInternalClock = 0 } |
enum | AhbPrescaler : uint32_t { Div1 = RCC_CFGR_HPRE_DIV1, Div2 = RCC_CFGR_HPRE_DIV2, Div4 = RCC_CFGR_HPRE_DIV4, Div8 = RCC_CFGR_HPRE_DIV8, Div16 = RCC_CFGR_HPRE_DIV16, Div64 = RCC_CFGR_HPRE_DIV64, Div128 = RCC_CFGR_HPRE_DIV128, Div256 = RCC_CFGR_HPRE_DIV256, Div512 = RCC_CFGR_HPRE_DIV512 } |
enum | Apb1Prescaler : uint32_t { Div1 = RCC_CFGR_PPRE1_DIV1, Div2 = RCC_CFGR_PPRE1_DIV2, Div4 = RCC_CFGR_PPRE1_DIV4, Div8 = RCC_CFGR_PPRE1_DIV8, Div16 = RCC_CFGR_PPRE1_DIV16 } |
enum | Apb2Prescaler : uint32_t { Div1 = RCC_CFGR_PPRE2_DIV1, Div2 = RCC_CFGR_PPRE2_DIV2, Div4 = RCC_CFGR_PPRE2_DIV4, Div8 = RCC_CFGR_PPRE2_DIV8, Div16 = RCC_CFGR_PPRE2_DIV16 } |
enum | Clock48Source { Hsi48 = 0, PllSai1Q = RCC_CCIPR_CLK48SEL_0, PllQ = RCC_CCIPR_CLK48SEL_1, Msi = RCC_CCIPR_CLK48SEL_1 | RCC_CCIPR_CLK48SEL_0 } |
enum | ClockOutputSource : uint32_t { Disable = 0b0000, SystemClock = (0b0001 << RCC_CFGR_MCOSEL_Pos), InternalClock = (0b0011 << RCC_CFGR_MCOSEL_Pos), ExternalClock = (0b0100 << RCC_CFGR_MCOSEL_Pos), ExternalCrystal = ExternalClock, Pll = (0b0101 << RCC_CFGR_MCOSEL_Pos), LowSpeedInternalClock = (0b0110 << RCC_CFGR_MCOSEL_Pos), LowSpeedExternalClock = (0b0111 << RCC_CFGR_MCOSEL_Pos) } |
enum | CanClockSource : uint32_t { Hse = 0, PllQ = RCC_CCIPR_FDCANSEL_0, Pclk = RCC_CCIPR_FDCANSEL_1 } |
enum | CanPrescaler : uint8_t { Div1 = 0b0000, Div2 = 0b0001, Div4 = 0b0010, Div6 = 0b0011, Div8 = 0b0100, Div10 = 0b0101, Div12 = 0b0110, Div14 = 0b0111, Div16 = 0b1000, Div18 = 0b1001, Div20 = 0b1010, Div22 = 0b1011, Div24 = 0b1100, Div26 = 0b1101, Div28 = 0b1110, Div30 = 0b1111 } |
FDCAN subsystem prescaler common to all FDCAN instances. | |
enum | ClockOutputPrescaler : uint32_t { Div1 = 0, Div2 = (1 << RCC_CFGR_MCOPRE_Pos), Div4 = (2 << RCC_CFGR_MCOPRE_Pos), Div8 = (3 << RCC_CFGR_MCOPRE_Pos), Div16 = (4 << RCC_CFGR_MCOPRE_Pos) } |
enum | VoltageScaling : uint32_t { Boost = 0, Scale1 = PWR_CR1_VOS_0, Scale2 = PWR_CR1_VOS_1 } |
Static Public Member Functions | |
static void | setCanClockSource (CanClockSource source) |
static bool | setCanPrescaler (CanPrescaler prescaler) |
Configure CAN subsystem prescaler. More... | |
static bool | enableInternalClock (uint32_t waitCycles=2048) |
static bool | enableExternalClock (uint32_t waitCycles=2048) |
static bool | enableExternalCrystal (uint32_t waitCycles=2048) |
static bool | enableLowSpeedInternalClock (uint32_t waitCycles=2048) |
static bool | enableLowSpeedExternalClock (uint32_t waitCycles=2048) |
static bool | enableLowSpeedExternalCrystal (uint32_t waitCycles=2048) |
static bool | enablePll (PllSource source, const PllFactors &pllFactors, uint32_t waitCycles=2048) |
static bool | disablePll (uint32_t waitCycles=2048) |
static bool | enableSystemClock (SystemClockSource src, uint32_t waitCycles=2048) |
static bool | enableRealTimeClock (RealTimeClockSource src) |
static bool | enableWatchdogClock (WatchdogClockSource) |
static void | setClock48Source (Clock48Source source) |
static bool | enableClockOutput (ClockOutputSource src, ClockOutputPrescaler div=ClockOutputPrescaler::Div1) |
static bool | setAhbPrescaler (AhbPrescaler prescaler) |
static bool | setApb1Prescaler (Apb1Prescaler prescaler) |
static bool | setApb2Prescaler (Apb2Prescaler prescaler) |
static bool | setVoltageScaling (VoltageScaling voltage, uint32_t waitCycles=2048) |
template<uint32_t Core_Hz, uint16_t Core_mV = 3300> | |
static uint32_t | setFlashLatency () |
template<uint32_t Core_Hz> | |
static void | updateCoreFrequency () |
template<class... Signals> | |
static void | connect () |
template<Peripheral peripheral> | |
static void | enable () |
template<Peripheral peripheral> | |
static bool | isEnabled () |
template<Peripheral peripheral> | |
static void | disable () |
Static Public Attributes | |
static constexpr uint32_t | LsiFrequency = 32'000 |
static constexpr uint32_t | HsiFrequency = 16'000'000 |
static constexpr uint32_t | BootFrequency = 16'000'000 |
Reset and Clock Control for STM32 devices.
This class abstracts access to clock settings on the STM32. You need to use this class to enable internal and external clock sources & outputs, set PLL parameters and AHB & APB prescalers. Don't forget to set the flash latencies.
|
strong |
|
static |
Disable PLL.
waitCycles | Number of cycles to wait for the pll to stabilise. Default: 2048. |
|
static |
Enable PLL.
source | Source select for PLL. If you are using HSE you must enable it first (see enableHse()). |
factors | Struct with all pll factors. |
waitCycles | Number of cycles to wait for the pll to stabilise. Default: 2048. |
|
static |
|
static |
Set flash latency for CPU frequency and voltage. Does nothing if CPU frequency is too high for the available voltage.
<=CPU_Frequency | flash latency has been set correctly. |
>CPU_Frequency | requested frequency too high for voltage. |