Flexible static memory controller.

Memory Map: 0x6000 0000 - 0x6fff ffff : Bank 1 4x NOR or [P]SRAM devices 0x7000 0000 - 0x7fff ffff : Bank 2 NAND Flash device 0x8000 0000 - 0x8fff ffff : Bank 3 NAND Flash device 0x9000 0000 - 0x9fff ffff : Bank 4 PC Card device each bank is 4x64 = 256 MB wide

NOR/PSRAM/SRAM Flash signals: CLK - Clock (for synchronous burst) A[25:0] - Address Bus AD[15:0] - 16-bit multiplexed, bidirectional address/data bus or data bus NE[x] - Chip select, x=1..4 NOE - Output enable NWE - Write enable NL(=NADV) - Latch enable (this signal is called address valid, NADV, by some NOR Flash devices) NWAIT - NOR Flash wait input signal to the FSMC NBL1 - Upper byte enable (memory signal name: NUB) NBL0 - Lowed byte enable (memory signal name: NLB)

Author

Fabian Greif