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modm API documentation
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#include <modm/platform/dma/dma_hal.hpp>
Public Typedefs | |
| using | IrqHandler = void (*)(void) |
Public Types | |
| enum | Channel { Channel1 = 0, Channel2, Channel3, Channel4, Channel5 } |
| enum | CircularMode : uint32_t { Disabled = 0, CircularMode::Enabled = DMA_CCR_CIRC } |
| enum | DataTransferDirection : uint32_t { DataTransferDirection::PeripheralToMemory = 0, DataTransferDirection::MemoryToPeripheral = DMA_CCR_DIR, DataTransferDirection::MemoryToMemory = DMA_CCR_MEM2MEM } |
| enum | InterruptEnable : uint32_t { TransferComplete = DMA_CCR_TCIE, HalfTransfer = DMA_CCR_HTIE, TransferError = DMA_CCR_TEIE } |
| enum | InterruptFlags : uint8_t { Global = 0b0001, TransferComplete = 0b0010, HalfTransferComplete = 0b0100, Error = 0b1000, All = 0b1111 } |
| enum | MemoryDataSize : uint32_t { Byte = 0, Bit8 = Byte, HalfWord = DMA_CCR_MSIZE_0, Bit16 = HalfWord, Word = DMA_CCR_MSIZE_1, Bit32 = Word } |
| enum | MemoryIncrementMode : uint32_t { Fixed = 0, MemoryIncrementMode::Increment = DMA_CCR_MINC } |
| enum | PeripheralDataSize : uint32_t { Byte = 0, Bit8 = Byte, HalfWord = DMA_CCR_PSIZE_0, Bit16 = HalfWord, Word = DMA_CCR_PSIZE_1, Bit32 = Word } |
| enum | PeripheralIncrementMode : uint32_t { Fixed = 0, PeripheralIncrementMode::Increment = DMA_CCR_PINC } |
| enum | Priority : uint32_t { Low = 0, Medium = DMA_CCR_PL_0, High = DMA_CCR_PL_1, VeryHigh = DMA_CCR_PL_1 | DMA_CCR_PL_0 } |
| enum | Request { Request0 = 0, Request1, Request2, Request3, Request4, Request5, Request6, Request7, Request8, Request9, Request10, Request11, Request12, Request13 } |
| enum | Signal : uint8_t { NoSignal, Ch1, Ch2, Ch3, Ch4, Com, Rx, Trig, Tx, Up } |
Public Member Functions | |
| MODM_FLAGS32 (InterruptEnable) | |
| MODM_FLAGS32 (InterruptFlags) | |
Static Public Member Functions | |
| static void | clearInterruptFlags (InterruptFlags flags, DmaBase::Channel ChannelID) |
| static uint32_t | getInterruptFlags () |
Static Public Attributes | |
| static constexpr uint32_t | DMA_BASE { getBaseAddress<ID>() } |
| DMA base register address. | |
| static constexpr uint32_t | CHANNEL_BASE { getChannelBaseAddress<ID>() } |
| DMA channel base register address. | |
| static constexpr uint32_t | CHANNEL_2_CHANNEL { 0x14 } |
| Register offset from channel to channel. | |
Static Protected Attributes | |
| static constexpr uint32_t | configmask |
| static constexpr uint32_t | memoryMask |
| static constexpr uint32_t | peripheralMask |
Hardware abstraction of DMA controller
| ID | The number of the DMA controller |
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In direct mode (if the FIFO is not used) MSIZE is forced by hardware to the same value as PSIZE
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| Enum Values | Documentation |
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| Increment | incremented according to MemoryDataSize |
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Peripheral signals that can be used in DMA channels
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