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modm::platform::Rcc Class Reference
Platform HAL » Reset and Clock Control (RCC)

#include <modm/platform/clock/rcc.hpp>

Classes

struct  PllFactors
 

Public Types

enum  PllSource : uint32_t {
  PllSource::Hsi = 0, InternalClock = Hsi, PllSource::Hse = RCC_CFGR_PLLSRC, ExternalClock = Hse,
  ExternalCrystal = Hse
}
 
enum  SystemClockSource : uint32_t {
  Hsi = RCC_CFGR_SW_HSI, Hse = RCC_CFGR_SW_HSE, InternalClock = Hsi, ExternalClock = Hse,
  ExternalCrystal = Hse, Pll = RCC_CFGR_SW_PLL
}
 
enum  RealTimeClockSource : uint32_t {
  Lsi = RCC_BDCR_RTCSEL_1, Lse = RCC_BDCR_RTCSEL_0, Hse = RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1, ExternalClock = Hse,
  ExternalCrystal = Hse, LowSpeedInternalClock = Lsi, LowSpeedExternalClock = Lse, LowSpeedExternalCrystal = Lse
}
 
enum  WatchdogClockSource : uint32_t { LowSpeedInternalClock = 0 }
 
enum  AhbPrescaler : uint32_t {
  Div1 = RCC_CFGR_HPRE_DIV1, Div2 = RCC_CFGR_HPRE_DIV2, Div4 = RCC_CFGR_HPRE_DIV4, Div8 = RCC_CFGR_HPRE_DIV8,
  Div16 = RCC_CFGR_HPRE_DIV16, Div64 = RCC_CFGR_HPRE_DIV64, Div128 = RCC_CFGR_HPRE_DIV128, Div256 = RCC_CFGR_HPRE_DIV256,
  Div512 = RCC_CFGR_HPRE_DIV512
}
 
enum  Apb1Prescaler : uint32_t {
  Div1 = RCC_CFGR_PPRE1_DIV1, Div2 = RCC_CFGR_PPRE1_DIV2, Div4 = RCC_CFGR_PPRE1_DIV4, Div8 = RCC_CFGR_PPRE1_DIV8,
  Div16 = RCC_CFGR_PPRE1_DIV16
}
 
enum  Apb2Prescaler : uint32_t {
  Div1 = RCC_CFGR_PPRE2_DIV1, Div2 = RCC_CFGR_PPRE2_DIV2, Div4 = RCC_CFGR_PPRE2_DIV4, Div8 = RCC_CFGR_PPRE2_DIV8,
  Div16 = RCC_CFGR_PPRE2_DIV16
}
 
enum  UsbPrescaler : uint32_t { UsbPrescaler::Div1 = RCC_CFGR_USBPRE, UsbPrescaler::Div1_5 = 0 }
 
enum  ClockOutputSource : uint32_t {
  SystemClock = RCC_CFGR_MCO_SYSCLK, InternalClock = RCC_CFGR_MCO_HSI, ExternalClock = RCC_CFGR_MCO_HSE, ExternalCrystal = RCC_CFGR_MCO_HSE,
  ClockOutputSource::Pll = RCC_CFGR_MCO_PLLCLK_DIV2
}
 

Static Public Member Functions

static bool enableInternalClock (uint32_t waitCycles=2048)
 
static bool enableExternalClock (uint32_t waitCycles=2048)
 
static bool enableExternalCrystal (uint32_t waitCycles=2048)
 
static bool enableLowSpeedInternalClock (uint32_t waitCycles=2048)
 
static bool enableLowSpeedExternalClock (uint32_t waitCycles=2048)
 
static bool enableLowSpeedExternalCrystal (uint32_t waitCycles=2048)
 
static bool enablePll (PllSource source, const PllFactors &pllFactors, uint32_t waitCycles=2048)
 
static bool disablePll (uint32_t waitCycles=2048)
 
static bool enableSystemClock (SystemClockSource src, uint32_t waitCycles=2048)
 
static bool enableRealTimeClock (RealTimeClockSource src)
 
static bool enableWatchdogClock (WatchdogClockSource)
 
static bool enableClockOutput (ClockOutputSource src)
 
static bool setAhbPrescaler (AhbPrescaler prescaler)
 
static bool setApb1Prescaler (Apb1Prescaler prescaler)
 
static bool setApb2Prescaler (Apb2Prescaler prescaler)
 
template<uint32_t Core_Hz, uint16_t Core_mV = 3300>
static uint32_t setFlashLatency ()
 
template<uint32_t Core_Hz>
static void updateCoreFrequency ()
 
template<class... Signals>
static void connect ()
 
template<Peripheral peripheral>
static void enable ()
 
template<Peripheral peripheral>
static bool isEnabled ()
 
template<Peripheral peripheral>
static void disable ()
 

Static Public Attributes

static constexpr uint32_t LsiFrequency = 40'000
 
static constexpr uint32_t HsiFrequency = 8'000'000
 
static constexpr uint32_t BootFrequency = 8'000'000
 

Detailed Description

Reset and Clock Control for STM32 devices.

This class abstracts access to clock settings on the STM32. You need to use this class to enable internal and external clock sources & outputs, set PLL parameters and AHB & APB prescalers. Don't forget to set the flash latencies.

Author
Niklas Hauser

Member Enumeration Documentation

enum modm::platform::Rcc::ClockOutputSource : uint32_t
strong
Enum ValuesDocumentation
Pll 

divided by 2

enum modm::platform::Rcc::PllSource : uint32_t
strong
Enum ValuesDocumentation
Hsi 

High speed internal clock (8 MHz)

Hse 

High speed external clock.

enum modm::platform::Rcc::UsbPrescaler : uint32_t
strong
Enum ValuesDocumentation
Div1 

do not divide

Div1_5 

divide by 1.5

Member Function Documentation

bool modm::platform::Rcc::disablePll ( uint32_t  waitCycles = 2048)
static

Disable PLL.

Parameters
waitCyclesNumber of cycles to wait for the pll to stabilise. Default: 2048.
bool modm::platform::Rcc::enablePll ( PllSource  source,
const PllFactors &  pllFactors,
uint32_t  waitCycles = 2048 
)
static

Enable PLL.

Parameters
sourceSource select for PLL. If you are using HSE you must enable it first (see enableHse()).
factorsStruct with all pll factors.
See also
PllFactors.
Parameters
waitCyclesNumber of cycles to wait for the pll to stabilise. Default: 2048.
template<uint32_t Core_Hz, uint16_t Core_mV = 3300>
static uint32_t modm::platform::Rcc::setFlashLatency ( )
static

Set flash latency for CPU frequency and voltage. Does nothing if CPU frequency is too high for the available voltage.

Returns
maximum CPU frequency for voltage.
Return Values
<=CPU_Frequencyflash latency has been set correctly.
>CPU_Frequencyrequested frequency too high for voltage.
The documentation for this class was generated from the following files: